1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to the fabrication of non-volatile memory devices.
2. Description of Related Art
Non-volatile MOS memory cells having a source and a drain disposed in a substrate and controlled by a gate may store data by trapping charges in a dielectric region of the gate. An unprogrammed cell may have substantially no charges trapped in the dielectric. A cell may be programmed by applying suitable programming voltages to the source, drain, and gate. The programming voltages may create an electric field in a channel between the source and drain that imparts energy to charges in the channel, enabling them to reach the dielectric region. The charges may become trapped in the dielectric region, thereby changing a threshold voltage of the cell. Forward and reverse reading methods are known by which the threshold voltage may be measured in order to determine whether a cell is programmed or unprogrammed. Some memory cells may store charge in separate portions of the dielectric region, thereby effectively storing more than one bit per cell.
With scaled-down geometries, parasitic effects that may negatively affect performance of devices employing non-volatile MOS memory cells must be considered. For example, a short channel effect and punch-through issues are known to be detrimental to memory cell operation. Lower programming efficiency when channel hot electron programming is employed may also result due to a degraded lateral electric field.
A need exists in the prior art for structures and methods that provide immunity from scaling issues in non-volatile MOS memory cells.